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<title>PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data </title></head>
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<h1>PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 60 /<em>r</em><sup>1</sup></p>
<p>PUNPCKLBW <em>mm, mm/m32</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Interleave low-order bytes from <em>mm</em> and <em>mm/m32</em> into <em>mm</em>.</td></tr>
<tr>
<td>
<p>66 0F 60 /<em>r</em></p>
<p>PUNPCKLBW <em>xmm1</em>,<em> xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Interleave low-order bytes from <em>xmm1</em> and <em>xmm2/m128</em> into <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>0F 61 /<em>r</em><sup>1</sup></p>
<p>PUNPCKLWD <em>mm, mm/m32</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Interleave low-order words from <em>mm</em> and <em>mm/m32</em> into <em>mm</em>.</td></tr>
<tr>
<td>
<p>66 0F 61 /<em>r</em></p>
<p>PUNPCKLWD <em>xmm1</em>,<em> xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Interleave low-order words from <em>xmm1</em> and <em>xmm2/m128</em> into <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>0F 62 /<em>r</em><sup>1</sup></p>
<p>PUNPCKLDQ <em>mm, mm/m32</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Interleave low-order doublewords from <em>mm </em>and <em>mm/m32</em> into <em>mm</em>.</td></tr>
<tr>
<td>
<p>66 0F 62 /<em>r</em></p>
<p>PUNPCKLDQ <em>xmm1</em>,<em> xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Interleave low-order doublewords from <em>xmm1 </em>and<em> xmm2/m128</em> into xmm1.</td></tr>
<tr>
<td>
<p>66 0F 6C /<em>r</em></p>
<p>PUNPCKLQDQ <em>xmm1</em>,<em> xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Interleave low-order quadword from <em>xmm1 </em>and <em>xmm2/m128</em> into <em>xmm1</em> register.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 60/r</p>
<p>VPUNPCKLBW <em>xmm1,xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Interleave low-order bytes from <em>xmm2</em> and <em>xmm3/m128</em> into <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 61/r</p>
<p>VPUNPCKLWD <em>xmm1,xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Interleave low-order words from <em>xmm2</em> and <em>xmm3/m128 </em>into<em> xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 62/r</p>
<p>VPUNPCKLDQ <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Interleave low-order doublewords from <em>xmm2 </em>and <em>xmm3/m128</em> into <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 6C/r</p>
<p>VPUNPCKLQDQ <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Interleave low-order quadword from <em>xmm2 </em>and <em>xmm3/m128</em> into <em>xmm1</em> register.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 60 /r</p>
<p>VPUNPCKLBW <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Interleave low-order bytes from <em>ymm2</em> and <em>ymm3/m256</em> into <em>ymm1</em> register.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 61 /r</p>
<p>VPUNPCKLWD <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Interleave low-order words from <em>ymm2</em> and <em>ymm3/m256</em> into <em>ymm1</em> register.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 62 /r</p>
<p>VPUNPCKLDQ<em> ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Interleave low-order doublewords from <em>ymm2 </em>and <em>ymm3/m256</em> into <em>ymm1</em> register.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 6C /r</p>
<p>VPUNPCKLQDQ <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Interleave low-order quadword from <em>ymm2 </em>and <em>ymm3/m256</em> into <em>ymm1</em> register.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.WIG 60 /r</p>
<p>VPUNPCKLBW xmm1 {k1}{z}, xmm2, xmm3/m128</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Interleave low-order bytes from xmm2 and xmm3/m128 into xmm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.WIG 61 /r</p>
<p>VPUNPCKLWD xmm1 {k1}{z}, xmm2, xmm3/m128</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Interleave low-order words from xmm2 and xmm3/m128 into xmm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W0 62 /r</p>
<p>VPUNPCKLDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Interleave low-order doublewords from xmm2 and xmm3/m128/m32bcst into xmm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W1 6C /r</p>
<p>VPUNPCKLQDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Interleave low-order quadword from zmm2 and zmm3/m512/m64bcst into zmm1 register subject to write mask k1.</td></tr></table>
<table>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.WIG 60 /r</p>
<p>VPUNPCKLBW ymm1 {k1}{z}, ymm2, ymm3/m256</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Interleave low-order bytes from ymm2 and ymm3/m256 into ymm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.WIG 61 /r</p>
<p>VPUNPCKLWD ymm1 {k1}{z}, ymm2, ymm3/m256</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Interleave low-order words from ymm2 and ymm3/m256 into ymm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W0 62 /r</p>
<p>VPUNPCKLDQ ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Interleave low-order doublewords from ymm2 and ymm3/m256/m32bcst into ymm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W1 6C /r</p>
<p>VPUNPCKLQDQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p>
<p>EVEX.NDS.512.66.0F.WIG 60/r</p>
<p>VPUNPCKLBW zmm1 {k1}{z}, zmm2, zmm3/m512</p>
<p>EVEX.NDS.512.66.0F.WIG 61/r</p>
<p>VPUNPCKLWD zmm1 {k1}{z}, zmm2, zmm3/m512</p></td>
<td>
<p>FV</p>
<p>FVM</p>
<p>FVM</p></td>
<td>
<p>V/V</p>
<p>V/V</p>
<p>V/V</p></td>
<td>
<p>AVX512VL AVX512F</p>
<p>AVX512BW Interleave low-order bytes from zmm2 and</p>
<p>AVX512BW Interleave low-order words from zmm2 and</p></td>
<td>
<p>Interleave low-order quadword from ymm2 and ymm3/m256/m64bcst into ymm1 register subject to write mask k1.</p>
<p>zmm3/m512 into zmm1 register subject to write mask k1.</p>
<p>zmm3/m512 into zmm1 register subject to write mask k1.</p></td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W0 62 /r</p>
<p>VPUNPCKLDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Interleave low-order doublewords from zmm2 and zmm3/m512/m32bcst into zmm1 register subject to write mask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W1 6C /r</p>
<p>VPUNPCKLQDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Interleave low-order quadword from zmm2 and zmm3/m512/m64bcst into zmm1 register subject to write mask k1.</td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FVM</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the destina-tion operand (first operand) and source operand (second operand) into the destination operand. (Figure 4-22 shows the unpack operation for bytes in 64-bit operands.). The high-order data elements are ignored.</p>
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<h3>Figure 4-22.  PUNPCKLBW Instruction Operation Using 64-bit Operands</h3>
<p>31</p>
<p>0</p>
<p>255</p>
<p>255</p>
<p>31</p>
<p>0</p>
<table class="exception-table">
<tr>
<td>X7</td>
<td>X6</td>
<td>X5</td>
<td>X4</td>
<td>X3</td>
<td>X2</td>
<td>X1</td>
<td>X0</td></tr></table>
<table class="exception-table">
<tr>
<td>Y7</td>
<td>Y6</td>
<td>Y5</td>
<td>Y4</td>
<td>Y3</td>
<td>Y2</td>
<td>Y1</td>
<td>Y0</td></tr></table>
<p>SRC</p>
<p>255</p>
<p>0</p>
<table class="exception-table">
<tr>
<td>Y5</td>
<td>X5</td>
<td>Y4</td>
<td>X4</td>
<td>Y1</td>
<td>X1</td>
<td>Y0</td>
<td>X0</td></tr></table>
<p>DEST</p>
<h3>Figure 4-23.  256-bit VPUNPCKLDQ Instruction Operation</h3>
<p>When the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.</p>
<p>The (V)PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the (V)PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the (V)PUNPCKLDQ instruction interleaves the low-order doubleword (or doublewords) of the source and destination operands, and the (V)PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination operands.</p>
<p>These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data elements from the original value in the destination operand. For example, with the (V)PUNPCKLBW instruction the high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKLWD instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).</p>
<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 32-bit memory location. The destination operand is an MMX technology register.</p>
<p>128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p>
<p>VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.</p>
<p>EVEX encoded VPUNPCKLDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.</p>
<p>EVEX encoded VPUNPCKLWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.</p>
<h2>Operation</h2>
<p><strong>PUNPCKLBW instruction with 64-bit operands:</strong></p>
<pre>    DEST[63:56] ← SRC[31:24];
    DEST[55:48] ← DEST[31:24];
    DEST[47:40] ← SRC[23:16];
    DEST[39:32] ← DEST[23:16];
    DEST[31:24] ← SRC[15:8];
    DEST[23:16] ← DEST[15:8];
    DEST[15:8] ← SRC[7:0];
    DEST[7:0] ← DEST[7:0];</pre>
<p><strong>PUNPCKLWD instruction with 64-bit operands:</strong></p>
<pre>    DEST[63:48] ← SRC[31:16];
    DEST[47:32] ← DEST[31:16];
    DEST[31:16] ← SRC[15:0];
    DEST[15:0] ← DEST[15:0];</pre>
<p><strong>PUNPCKLDQ instruction with 64-bit operands:</strong></p>
<pre>    DEST[63:32] ← SRC[31:0];
    DEST[31:0] ← DEST[31:0];
INTERLEAVE_BYTES_512b (SRC1, SRC2)
TMP_DEST[255:0] (cid:197) INTERLEAVE_BYTES_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] (cid:197) INTERLEAVE_BYTES_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_BYTES_256b (SRC1, SRC2)
DEST[7:0] (cid:197) SRC1[7:0]
DEST[15:8] (cid:197) SRC2[7:0]
DEST[23:16] (cid:197) SRC1[15:8]
DEST[31:24] (cid:197) SRC2[15:8]
DEST[39:32] (cid:197) SRC1[23:16]
DEST[47:40] (cid:197) SRC2[23:16]
DEST[55:48] (cid:197) SRC1[31:24]
DEST[63:56] (cid:197) SRC2[31:24]
DEST[71:64] (cid:197) SRC1[39:32]
DEST[79:72] (cid:197) SRC2[39:32]
DEST[87:80] (cid:197) SRC1[47:40]
DEST[95:88] (cid:197) SRC2[47:40]
DEST[103:96] (cid:197) SRC1[55:48]
DEST[111:104] (cid:197) SRC2[55:48]
DEST[119:112] (cid:197) SRC1[63:56]
DEST[127:120] (cid:197) SRC2[63:56]
DEST[135:128] (cid:197) SRC1[135:128]
DEST[143:136] (cid:197) SRC2[135:128]
DEST[151:144] (cid:197) SRC1[143:136]
DEST[159:152] (cid:197) SRC2[143:136]
DEST[167:160] (cid:197) SRC1[151:144]
DEST[175:168] (cid:197) SRC2[151:144]
DEST[183:176] (cid:197) SRC1[159:152]
DEST[191:184] (cid:197) SRC2[159:152]
DEST[199:192] (cid:197) SRC1[167:160]
DEST[207:200] (cid:197) SRC2[167:160]
DEST[215:208] (cid:197) SRC1[175:168]
DEST[223:216] (cid:197) SRC2[175:168]
DEST[231:224] (cid:197) SRC1[183:176]
DEST[239:232] (cid:197) SRC2[183:176]
DEST[247:240] (cid:197) SRC1[191:184]
DEST[255:248] (cid:197) SRC2[191:184]
INTERLEAVE_BYTES (SRC1, SRC2)
DEST[7:0] (cid:197) SRC1[7:0]
DEST[15:8] (cid:197) SRC2[7:0]
DEST[23:16] (cid:197) SRC2[15:8]
DEST[31:24] (cid:197) SRC2[15:8]
DEST[39:32] (cid:197) SRC1[23:16]
DEST[47:40] (cid:197) SRC2[23:16]
DEST[55:48] (cid:197) SRC1[31:24]
DEST[63:56] (cid:197) SRC2[31:24]
DEST[71:64] (cid:197) SRC1[39:32]
DEST[79:72] (cid:197) SRC2[39:32]
DEST[87:80] (cid:197) SRC1[47:40]
DEST[95:88] (cid:197) SRC2[47:40]
DEST[103:96] (cid:197) SRC1[55:48]
DEST[111:104] (cid:197) SRC2[55:48]
DEST[119:112] (cid:197) SRC1[63:56]
DEST[127:120] (cid:197) SRC2[63:56]
INTERLEAVE_WORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] (cid:197) INTERLEAVE_WORDS_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] (cid:197) INTERLEAVE_WORDS_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[15:0] (cid:197) SRC1[15:0]
DEST[31:16] (cid:197) SRC2[15:0]
DEST[47:32] (cid:197) SRC1[31:16]
DEST[63:48] (cid:197) SRC2[31:16]
DEST[79:64] (cid:197) SRC1[47:32]
DEST[95:80] (cid:197) SRC2[47:32]
DEST[111:96] (cid:197) SRC1[63:48]
DEST[127:112] (cid:197) SRC2[63:48]
DEST[143:128] (cid:197) SRC1[143:128]
DEST[159:144] (cid:197) SRC2[143:128]
DEST[175:160] (cid:197) SRC1[159:144]
DEST[191:176] (cid:197) SRC2[159:144]
DEST[207:192] (cid:197) SRC1[175:160]
DEST[223:208] (cid:197) SRC2[175:160]
DEST[239:224] (cid:197) SRC1[191:176]
DEST[255:240] (cid:197) SRC2[191:176]
INTERLEAVE_WORDS (SRC1, SRC2)
DEST[15:0] (cid:197) SRC1[15:0]
DEST[31:16] (cid:197) SRC2[15:0]
DEST[47:32] (cid:197) SRC1[31:16]
DEST[63:48] (cid:197) SRC2[31:16]
DEST[79:64] (cid:197) SRC1[47:32]
DEST[95:80] (cid:197) SRC2[47:32]
DEST[111:96] (cid:197) SRC1[63:48]
DEST[127:112] (cid:197) SRC2[63:48]
INTERLEAVE_DWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] (cid:197) INTERLEAVE_DWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] (cid:197) INTERLEAVE_DWORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[31:0] (cid:197) SRC1[31:0]
DEST[63:32] (cid:197) SRC2[31:0]
DEST[95:64] (cid:197) SRC1[63:32]
DEST[127:96] (cid:197) SRC2[63:32]
DEST[159:128] (cid:197) SRC1[159:128]
DEST[191:160] (cid:197) SRC2[159:128]
DEST[223:192] (cid:197) SRC1[191:160]
DEST[255:224] (cid:197) SRC2[191:160]
INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[31:0] (cid:197) SRC1[31:0]
DEST[63:32] (cid:197) SRC2[31:0]
DEST[95:64] (cid:197) SRC1[63:32]
DEST[127:96] (cid:197) SRC2[63:32]
INTERLEAVE_QWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] (cid:197) INTERLEAVE_QWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] (cid:197) INTERLEAVE_QWORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[63:0] (cid:197) SRC1[63:0]
DEST[127:64] (cid:197) SRC2[63:0]
DEST[191:128] (cid:197) SRC1[191:128]
DEST[255:192] (cid:197) SRC2[191:128]
INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[63:0] (cid:197) SRC1[63:0]
DEST[127:64] (cid:197) SRC2[63:0]</pre>
<p><strong>PUNPCKLBW</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)</pre>
<p><strong>VPUNPCKLBW (VEX.128 encoded instruction)</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_BYTES(SRC1, SRC2)
DEST[511:127] (cid:197)0</pre>
<p><strong>VPUNPCKLBW (VEX.256 encoded instruction)</strong></p>
<pre>DEST[255:0] (cid:197)INTERLEAVE_BYTES_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] (cid:197)0</pre>
<p><strong>VPUNPCKLBW (EVEX.512 encoded instruction)</strong></p>
<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] (cid:197) TMP_DEST[i+7:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+7:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                               ; zeroing-masking
                         DEST[i+7:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0
DEST[511:0] (cid:197) INTERLEAVE_BYTES_512b(SRC1, SRC2)</pre>
<p><strong>PUNPCKLWD</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_WORDS(DEST, SRC)
DEST[255:127] (Unmodified)</pre>
<p><strong>VPUNPCKLWD (VEX.128 encoded instruction)</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_WORDS(SRC1, SRC2)
DEST[511:127] (cid:197)0</pre>
<p><strong>VPUNPCKLWD (VEX.256 encoded instruction)</strong></p>
<pre>DEST[255:0] (cid:197)INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] (cid:197)0</pre>
<p><strong>VPUNPCKLWD (EVEX.512 encoded instruction)</strong></p>
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] (cid:197) TMP_DEST[i+15:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                              ; zeroing-masking
                         DEST[i+15:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0
DEST[511:0] (cid:197) INTERLEAVE_WORDS_512b(SRC1, SRC2)</pre>
<p><strong>PUNPCKLDQ</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>VPUNPCKLDQ (VEX.128 encoded instruction)</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] (cid:197)0</pre>
<p><strong>VPUNPCKLDQ (VEX.256 encoded instruction)</strong></p>
<pre>DEST[255:0] (cid:197)INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] (cid:197)0</pre>
<p><strong>VPUNPCKLDQ (EVEX encoded instructions)</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] (cid:197) SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] (cid:197) SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 128
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] (cid:197) TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                              ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST511:0] (cid:197)INTERLEAVE_DWORDS_512b(SRC1, SRC2)
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>PUNPCKLQDQ</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>VPUNPCKLQDQ (VEX.128 encoded instruction)</strong></p>
<pre>DEST[127:0] (cid:197)INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] (cid:197)0</pre>
<p><strong>VPUNPCKLQDQ (VEX.256 encoded instruction)</strong></p>
<pre>DEST[255:0] (cid:197)INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] (cid:197)0</pre>
<p><strong>VPUNPCKLQDQ (EVEX encoded instructions)</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] (cid:197) SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] (cid:197) SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 128
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] (cid:197) INTERLEAVE_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] (cid:197) TMP_DEST[i+63:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                               ; zeroing-masking
                         DEST[i+63:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalents</h2>
<p>VPUNPCKLBW __m512i _mm512_unpacklo_epi8(__m512i a, __m512i b);</p>
<p>VPUNPCKLBW __m512i _mm512_mask_unpacklo_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLBW __m512i _mm512_maskz_unpacklo_epi8( __mmask64 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLBW __m256i _mm256_mask_unpacklo_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLBW __m256i _mm256_maskz_unpacklo_epi8( __mmask32 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLBW __m128i _mm_mask_unpacklo_epi8(v s, __mmask16 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLBW __m128i _mm_maskz_unpacklo_epi8( __mmask16 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLWD __m512i _mm512_unpacklo_epi16(__m512i a, __m512i b);</p>
<p>VPUNPCKLWD __m512i _mm512_mask_unpacklo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLWD __m512i _mm512_maskz_unpacklo_epi16( __mmask32 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLWD __m256i _mm256_mask_unpacklo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLWD __m256i _mm256_maskz_unpacklo_epi16( __mmask16 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLWD __m128i _mm_mask_unpacklo_epi16(v s, __mmask8 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLWD __m128i _mm_maskz_unpacklo_epi16( __mmask8 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLDQ __m512i _mm512_unpacklo_epi32(__m512i a, __m512i b);</p>
<p>VPUNPCKLDQ __m512i _mm512_mask_unpacklo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLDQ __m512i _mm512_maskz_unpacklo_epi32( __mmask16 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLDQ __m256i _mm256_mask_unpacklo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLDQ __m256i _mm256_maskz_unpacklo_epi32( __mmask8 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLDQ __m128i _mm_mask_unpacklo_epi32(v s, __mmask8 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLDQ __m128i _mm_maskz_unpacklo_epi32( __mmask8 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLQDQ __m512i _mm512_unpacklo_epi64(__m512i a, __m512i b);</p>
<p>VPUNPCKLQDQ __m512i _mm512_mask_unpacklo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLQDQ __m512i _mm512_maskz_unpacklo_epi64( __mmask8 k, __m512i a, __m512i b);</p>
<p>VPUNPCKLQDQ __m256i _mm256_mask_unpacklo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLQDQ __m256i _mm256_maskz_unpacklo_epi64( __mmask8 k, __m256i a, __m256i b);</p>
<p>VPUNPCKLQDQ __m128i _mm_mask_unpacklo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);</p>
<p>VPUNPCKLQDQ __m128i _mm_maskz_unpacklo_epi64( __mmask8 k, __m128i a, __m128i b);</p>
<p>PUNPCKLBW:__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)</p>
<p>(V)PUNPCKLBW:__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)</p>
<p>VPUNPCKLBW:__m256i _mm256_unpacklo_epi8 (__m256i m1, __m256i m2)</p>
<p>PUNPCKLWD:__m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)</p>
<p>(V)PUNPCKLWD:__m128i _mm_unpacklo_epi16 (__m128i m1, __m128i m2)</p>
<p>VPUNPCKLWD:__m256i _mm256_unpacklo_epi16 (__m256i m1, __m256i m2)</p>
<p>PUNPCKLDQ:__m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)</p>
<p>(V)PUNPCKLDQ:__m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2)</p>
<p>VPUNPCKLDQ:__m256i _mm256_unpacklo_epi32 (__m256i m1, __m256i m2)</p>
<p>(V)PUNPCKLQDQ:__m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2)</p>
<p>VPUNPCKLQDQ:__m256i _mm256_unpacklo_epi64 (__m256i m1, __m256i m2)</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Numeric Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded VPUNPCKLDQ/QDQ, see Exceptions Type E4NF.</td></tr>
<tr>
<td>EVEX-encoded VPUNPCKLBW/WD, see Exceptions Type E4NF.nb.</td></tr></table></body></html>